The present invention relates to a semiconductor design technology, and more particularly, to a technology for monitoring a state of a specific fuse.
Semiconductor devices and semiconductor memory devices may include a fuse circuit for changing an internal setup or programming a repair address. A fuse included in a fuse circuit stores an address and specific setup information through a fuse programming. When a laser beam or electrical stress is applied to a fuse, an electrical connection characteristic of the fuse is changed and therefore an electrical resistance is changed. Specific information is programmed using the change of an electric connection state, that is, a short state or an open state.
A laser blowing type fuse whose connection state is cut using a laser beam is generally called a physical fuse type and is used in a wafer level that is prior to fabrication of a semiconductor device into a package. In a package level, an electrical method is used, instead of a physical method using a laser beam. A fuse programmable in a package level is generally called an electrical fuse. The electrical fuse is programmed by changing an electrical connection state through application of an electrical stress. The electrical fuse may be classified into an anti-type fuse (hereinafter, referred to as an antifuse) changing an open state to a short state, and a blowing-type fuse changing a short state to an open state. Various types of fuses are selectively used, considering characteristics or area of semiconductor device and semiconductor memory devices.
Generally, a fuse circuit includes a plurality of fuse set units. In the case of a fuse circuit for programming an address, a specific address can be programmed in each fuse set. That is, the fuse circuit stores addresses corresponding to electrical connection states of a plurality of address fuses included in the fuse sets. A basic unit for storing one address is referred to as a fuse set unit.
FIG. 1 is a block diagram of a typical fuse set unit.
Referring to FIG. 1, a fuse set unit includes an enable fuse unit 101, an address fuse unit 102, and a signal combination unit 103. The address fuse unit 102 compares address information programmed in a plurality of address fuses with address bit signals of input addresses ADDR<0:N> and outputs a plurality of comparison result signals HIT<0:N>. The signal combination unit 103 combines the comparison result signals HIT<0:N> under the control of the enable fuse unit 101 and outputs a combination signal HITB. The enable fuse unit 101 outputs an enable signal ENABLE corresponding to an electrical connection state of an enable fuse. The enable signal ENABLE is used to control the signal combination unit 103. That is, when the enable fuse is cut, the enable signal ENABLE is activated and the signal combination unit 103 combines the comparison result signals HIT<0:N> of the address fuse unit 102 to output the combination signal HITB.
FIG. 2 is a circuit diagram of the enable fuse unit 101 of FIG. 1.
Referring to FIG. 2, the enable fuse unit 101 includes a PMOS transistor MP1, a fuse, a first NMOS transistor MN1, a first inverter INV1, a second NMOS transistor MN2, a NOR gate NOR1, and a second inverter INV2. The PMOS transistor MP1 is connected between a power supply voltage terminal VDD and a first node N1 and is controlled by a power-up signal PWRUP. The fuse is connected between the first node N1 and a second node N2. The first NMOS transistor MN1 is connected between a ground voltage terminal VSS and the second node N2 and is controlled by the power-up signal PWRUP. The first inverter INV1 receives a signal of the second node N2. The second NMOS transistor MN2 is connected between the second node N2 and the ground voltage terminal VSS and is controlled by an output signal of the first inverter INV1. The NOR gate NOR1 receives a test mode signal TEST_MODE and the output signal of the first inverter INV1. The second inverter INV2 receives an output signal of the NOR gate NOR1 to output the enable signal ENABLE.
An operation of the enable fuse unit will be described below.
The power-up signal PWRUP changes to a low level when an external power supply voltage is stabilized, and the test mode signal TEST_MODE maintains a high level when a test mode is enabled.
In a normal mode where the test mode signal TEST_MODE maintains a low level, the NOR gate NOR1 inverts the output signal of the first inverter INV1. The second inverter INV2 inverts the output signal of the NOR gate NOR1 and outputs the inverted signal as the enable signal ENABLE. If the fuse is not cut, the first PMOS transistor MP1 is turned on in response to the power-up signal PWRUP and thus the voltage level of the second node N2 increases. As a result, the enable signal ENABLE of a low level is outputted. If the fuse is cut, the voltage level of the second node N2 becomes an initial low level and is kept at the low level by a latch implemented with the second NMOS transistor MN2 and the first inverter INV1.
As a result, the enable signal ENABLE is activated to a high level. That is, when the fuse is cut in the normal mode, the enable signal ENABLE is activated to a high level.
Meanwhile, in a test mode where the test mode signal TEST_MODE is at a high level, the NOR gate NOR1 outputs a low level, without regard to the output signal of the first inverter INV1 and thus the enable signal ENABLE of a high level is outputted. That is, in the test mode, the enable signal ENABLE is activated to a high level, without regard to the cutting of the fuse.
FIG. 3 is a block diagram of a conventional fuse circuit of a semiconductor device.
Referring to FIG. 3, the conventional fuse circuit includes a plurality of fuse set units 301 to 306 for comparing input addresses ADDR<0:N> with address information programmed according to fuse cutting states.
When the test mode signal TEST_MODE is activated to a high level and thus the semiconductor device operates in a test mode, the fuse set units 301 to 306 are simultaneously enabled in response to the test mode signal TEST_MODE. In the test mode, it is detected whether the address fuses included in the fuse set units 301 to 306 are defective. In the conventional fuse circuit, the fuse set units 301 to 306 are simultaneously enabled when the test mode signal TEST_MODE is activated, and the defective address fuses are detected by comparing the programmed addresses with the input addresses ADDR<0:N>.
In this way, since the fuse set units are simultaneously enabled in the test mode, the conventional fuse circuit can detect whether the defective address fuse exists in the fuse set units 301 to 306 as a whole. However, the conventional fuse circuit cannot detect a fuse set unit individually where a defective address fuse exists. Moreover, the conventional fuse circuit cannot detect which address fuse is defective in the corresponding fuse set unit.